Why is the phase detector modeled as K_d sin(φ_ref − φ_VCO)?

A four-quadrant analog multiplier fed with two sinusoids produces a double-frequency term plus a baseband term proportional to sin of the phase difference. After ignoring the high-frequency component (implicit low-pass), the sinusoidal PD characteristic is the standard small-angle teaching model; near lock it behaves approximately linearly.

What is the difference between lock range and capture range here?

Informally, lock range is the frequency offset magnitude for which a loop already in lock can continue tracking as parameters change, while capture range is the offset from which an unlocked loop can still pull in without slipping cycles. This simulator does not compute those intervals analytically; instead you sweep ω_fr, ω_ref steps, and gains to see when φ_e remains bounded and the sine traces stay aligned.

Why does K_i = 0 often leave a frequency error at the end of the run?

With only proportional action, the loop must generate a nonzero average control u to sustain a different ω_VCO from ω_fr when ω_ref demands a new locked frequency. That typically requires a persistent phase offset at the PD output in this simplified model—classic type-I behavior—whereas integral action can drive the average phase error toward zero for a type-II loop under many conditions.

Is this suitable for designing a real RF PLL?

No. Real PLLs include divider ratios, charge-pump and loop-filter dynamics, reference and VCO noise, spurs, and nonlinear acquisition phenomena. Treat this page as a qualitative sandbox for the core feedback structure and the roles of K_p, K_i, and K_v.

PLL (Phase-Locked Loop)

Discrete-time analog-style PLL: multiplier PD e = K_d sin(φ_ref − φ_VCO), PI loop filter, VCO ω = ω_fr + K_v u; step ω_ref to explore lock, capture, and steady-state phase error.

Live graphs

About this model

A phase-locked loop (PLL) synchronizes a controlled oscillator to a reference by closing a feedback loop through a phase detector and a loop filter. This page uses a compact discrete-time caricature of an analog second-order PLL: the reference integrates a piecewise-constant angular frequency ω_ref(t) to produce φ_ref; the voltage-controlled oscillator (VCO) integrates ω_VCO = ω_fr + K_v u where ω_fr is the free-running offset and u is the loop-filter output. A multiplier-style phase detector yields e = K_d sin(φ_ref − φ_VCO), and a proportional–integral (PI) loop filter implements u = K_p e + ∫ K_i e dt with simple Euler accumulation. When gains are chosen in a stable range, the loop can lock so that ω_VCO tracks ω_ref and the wrapped phase error φ_e = wrap(φ_ref − φ_VCO) stays small; stepping ω_ref illustrates transient pull-in/capture behavior versus loss of lock or prolonged ringing. Setting K_i = 0 recovers a type-I loop where a frequency offset typically forces a nonzero steady-state phase error. The model omits delay, higher-order filtering, cycle slips as discrete events, and digital-specific blocks (N-dividers, PFD/CP), but it is enough to build intuition for lock, loop bandwidth, and the trade-off between damping and integral action.

Who it's for: Undergraduate signals-and-systems or communications students learning FM demodulation, clock recovery, and control-style frequency tracking; anyone who wants a hands-on feel for PD gain, loop filter poles, and VCO tuning sensitivity.

Key terms

Phase-locked loop
VCO
Phase detector
Loop filter
Lock range
Capture range
Type-I vs type-II loop
PI control

How it works

Analog PLL model: reference sin φ_ref with piecewise-constant ω_ref, VCO integrates ω = ω_fr + K_v u, multiplier phase detector gives e = K_d sin(φ_ref − φ_VCO), and a PI loop filter u = K_p e + ∫ K_i e drives the VCO toward lock (ω tracks ω_ref, φ_e small). Step the reference to see capture and steady-state error; turning K_i to zero mimics a type-I loop with residual phase offset under frequency detuning.

Key equations

φ̇_ref = ω_ref(t), φ̇_VCO = ω_fr + K_v u

e = K_d sin(φ_ref − φ_VCO), u = K_p e + ∫ K_i e dt

Frequently asked questions

Why is the phase detector modeled as K_d sin(φ_ref − φ_VCO)?: A four-quadrant analog multiplier fed with two sinusoids produces a double-frequency term plus a baseband term proportional to sin of the phase difference. After ignoring the high-frequency component (implicit low-pass), the sinusoidal PD characteristic is the standard small-angle teaching model; near lock it behaves approximately linearly.
What is the difference between lock range and capture range here?: Informally, lock range is the frequency offset magnitude for which a loop already in lock can continue tracking as parameters change, while capture range is the offset from which an unlocked loop can still pull in without slipping cycles. This simulator does not compute those intervals analytically; instead you sweep ω_fr, ω_ref steps, and gains to see when φ_e remains bounded and the sine traces stay aligned.
Why does K_i = 0 often leave a frequency error at the end of the run?: With only proportional action, the loop must generate a nonzero average control u to sustain a different ω_VCO from ω_fr when ω_ref demands a new locked frequency. That typically requires a persistent phase offset at the PD output in this simplified model—classic type-I behavior—whereas integral action can drive the average phase error toward zero for a type-II loop under many conditions.
Is this suitable for designing a real RF PLL?: No. Real PLLs include divider ratios, charge-pump and loop-filter dynamics, reference and VCO noise, spurs, and nonlinear acquisition phenomena. Treat this page as a qualitative sandbox for the core feedback structure and the roles of K_p, K_i, and K_v.

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Live graphs

About this model

How it works

Key equations

Frequently asked questions

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Live graphs

About this model

How it works

Key equations

Frequently asked questions